• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    PURPOSE: A TFT and a fabricating method thereof are provided to simplify its fabrication process by using a single-layered amorphous silicon thin film to form a channel layer. CONSTITUTION: A TFT includes a plurality of gate electrodes, an active layer, a doping barrier pattern, a source electrode, and a drain electrode. The gate electrodes(137) are formed on a substrate. The active layer(157) includes a semiconductor pattern part, the first doping part, and the second doping part. The semiconductor pattern part is formed on a top part of the gate electrode in order to insulate the gate electrode. The first doping part is used for supplying electrons to the semiconductor pattern part. The second doping part is used for receiving the electrons from the semiconductor pattern part. The doping barrier pattern is formed on a top portion of the semiconductor pattern part. The source electrode(173) is connected to the first doping part. The drain electrode(176) is connected to the second doping part.
    公开号:KR20040044726A
    申请号:KR1020020072876
    申请日:2002-11-21
    公开日:2004-05-31
    发明作者:김봉주；윤주선；양용호；태승규；박진석；김현영
    申请人:삼성전자주식회사；
    IPC主号:
    专利说明:

    Thin film transistor and method for manufacturing same {THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THEREOF}
    [11] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a method for manufacturing the same, and more particularly, to a thin film transistor and a method for manufacturing the same, which have improved reliability by changing the structure of a channel layer for switching the flow of electrons.
    [12] In general, a thin film transistor (TFT) is an element that switches the flow of electrons by using a plurality of thin films having unique characteristics.
    [13] The field of use of such a thin film transistor is very large. For example, thin film transistors have been developed and utilized as liquid crystal display devices, peripheral devices such as laser printer heads, and image sensors such as scanners by using advantages that can be formed on substrates other than silicon substrates. In particular, recently, a technique of applying amorphous silicon, which can be processed at a low temperature, to a thin film transistor has been developed.
    [14] Thin film transistors have a very simple structure that can be fabricated in just a few layers. For example, the thin film transistor includes a gate electrode in a thin film form, a gate insulating layer insulating the gate electrode, a channel layer formed on an upper surface of the gate insulating layer, a source electrode connected to the channel layer, and a drain electrode.
    [15] Various thin film transistors have been developed.
    [16] U.S. Patent No. 6,395,652 "Method of manufacturing thin film transistor", the n + amorphous silicon thin film is deposited on the upper surface of the amorphous silicon thin film and amorphous silicon thin film, the n + amorphous silicon thin film is patterned with the channel layer structure is disclosed.
    [17] However, the channel layer fabricated by the above method has a problem in that when the n + amorphous silicon thin film is not completely patterned, current is leaked by the n + amorphous silicon thin film remaining on the surface of the amorphous silicon thin film because it is not completely patterned. .
    [18] In addition, when the n + amorphous silicon thin film is over-etched in the process of patterning the n + amorphous silicon thin film, the amorphous silicon thin film disposed under the n + amorphous silicon thin film is also etched together to deteriorate the current characteristics of the amorphous silicon thin film. Has
    [19] United States Patent No. 6,130,729 "Method of making an AMLCD where the etch stopper is formed without first preparing a pattern mask" includes problems caused by the use of an etch stopper to prevent the n + amorphous silicon thin film from fully etching and The technical contents that overcome the problems caused by etching are included.
    [20] However, a method of manufacturing a thin film transistor using an etch stopper has a large contact resistance because a part of the insulating film used to fabricate an etch stopper remains at the interface between the amorphous silicon thin film and the n + amorphous silicon thin film during the manufacture of the etch stopper. There is an increasing problem.
    [21] Accordingly, the present invention has been made in view of such conventional problems, and a first object of the present invention is to provide a thin film transistor having high reliability and a shortened manufacturing process.
    [22] It is a second object of the present invention to provide a method for manufacturing a thin film transistor having high reliability and a reduced manufacturing process.
    [1] 1 is a conceptual diagram of a thin film transistor according to an embodiment of the present invention.
    [2] 2 is a process diagram illustrating that a gate metal is formed on a substrate according to an embodiment of the present invention.
    [3] 3 is a process diagram illustrating a gate electrode formed on a substrate according to an embodiment of the present invention.
    [4] 4 is a process diagram illustrating an insulating film for insulating the gate electrode according to an exemplary embodiment of the present invention.
    [5] FIG. 5 is a process diagram illustrating an amorphous silicon thin film and an ion stopper thin film formed on an upper surface of an insulating film according to an embodiment of the present invention.
    [6] 6 is a conceptual diagram illustrating a process of patterning an ion stopper thin film according to an embodiment of the present invention.
    [7] 7 is a process diagram illustrating an ion stopper patterned from an ion stopper thin film according to an embodiment of the present invention.
    [8] FIG. 8 is a flowchart illustrating ion implantation performed on an amorphous silicon thin film having an ion stopper according to an embodiment of the present invention.
    [9] FIG. 9 is a process diagram illustrating a source / drain metal formed on an upper surface of a semiconductor pattern portion, a first impurity implanted portion, and a second impurity implanted portion according to an embodiment of the present invention.
    [10] 10 is a cross-sectional view illustrating a profile of a thin film transistor according to an exemplary embodiment of the present invention.
    [23] In order to realize the first object of the present invention, the present invention provides a plurality of gate electrodes formed on a substrate, a semiconductor pattern portion formed on an upper portion of the gate electrode so as to be insulated from the gate electrode, and a first impurity injection for supplying electrons to the semiconductor pattern portion. A thin film transistor includes an active layer including a second impurity implantation unit receiving electrons from a semiconductor pattern unit, a source electrode connected to the first impurity implantation unit, and a drain electrode connected to the second impurity implantation unit.
    [24] The present invention also provides a method for forming a plurality of gate electrodes on a substrate, the semiconductor pattern portion formed on an upper portion of the gate electrode so as to be insulated from the gate electrode, and a semiconductor pattern portion supplying electrons to the semiconductor pattern portion. Forming an active layer including a first impurity implantation unit and a second impurity implantation unit receiving electrons from the semiconductor pattern unit; forming a source electrode connected to the first impurity implantation unit and a drain electrode connected to the second impurity implantation unit It provides a method of manufacturing a thin film transistor comprising a.
    [25] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
    [26] 1 is a conceptual diagram of a thin film transistor according to an embodiment of the present invention. 10 is a cross-sectional view illustrating a profile of a thin film transistor according to an exemplary embodiment of the present invention.
    [27] 1 or 10, the thin film transistor 200 includes a gate electrode 137, an active layer 157, a source electrode 173, and a drain electrode 176. Reference numeral 100 is a substrate 100 on which the thin film transistor 200 is formed. In one embodiment, the substrate 100 is a transparent glass substrate.
    [28] In one embodiment, the gate electrode 137 includes a chromium thin film 125 patterned such that its long axis extends in the Y-axis direction defined in FIG. 1, and an aluminum thin film 135 disposed on an upper surface of the chromium thin film 125.
    [29] A channel turn-on voltage having a positive polarity is applied to the gate electrode 137. The channel turn-on voltage is a threshold voltage (V th ) sufficient to form a channel in the active layer 157 to be described later.
    [30] The channel turn-on voltage is supplied from the gate line 210 connected to the gate electrode 137 formed in the X-axis direction defined in FIG. 1.
    [31] Referring to FIG. 1 or 10, the active layer 157 includes a semiconductor pattern portion 156, a first impurity injector 153, and a second impurity injector 159.
    [32] In this case, the semiconductor pattern part 156, the first impurity injector 153, and the second impurity injector 159 are all formed on the same layer. The first impurity injector 153 supplies electrons to the semiconductor pattern unit 156, and the second impurity injector 159 receives electrons from the semiconductor pattern unit 156.
    [33] The semiconductor pattern part 156, the first impurity injector 153, and the second impurity injector 159 are insulated from the gate line 210 and the gate electrode 137 through the insulating layer 145.
    [34] The semiconductor pattern portion 156 is formed on the gate electrode 137. The semiconductor pattern portion 156 and the gate electrode 137 are insulated from each other. The semiconductor pattern portion 156 is made of amorphous silicon.
    [35] The first impurity implantation part 153 is connected to the first end 155 of the semiconductor pattern part 156. The first impurity implanter 153 is a first n + amorphous silicon thin film in which n + ions, which are dopants, are implanted into amorphous silicon.
    [36] The second impurity implantation portion 159 is connected to the second end 155 of the semiconductor pattern portion 156. The second impurity implantation unit 159 is a second n + amorphous silicon thin film in which n + ions, which are dopants, are implanted into amorphous silicon.
    [37] In order to form the first impurity implantation unit 153, the semiconductor pattern unit 156, and the second impurity implantation unit 159 having such a configuration on the same layer, an ion stopper ( 165 is formed. The ion stopper 165 prevents n + ions scanned from the outside from being injected into the semiconductor pattern portion 156.
    [38] Part or all of the source electrode 173 is connected to an upper surface of the first impurity injector 153. The source electrode 173 is made of aluminum or an aluminum alloy, and extends in the X-axis direction shown in FIG. 1 to be connected to the first impurity injector 153.
    [39] The data line 220 shown in FIG. 1 is connected to the source electrode 173. The data line 220 applies a voltage having a predetermined magnitude to the source electrode 173.
    [40] A part or all of the drain electrode 176 is connected to the second impurity injection part 153 so as to be insulated from the source electrode 173. The drain electrode 176 is made of aluminum or an aluminum alloy, and extends in the X-axis direction shown in FIG. 1 to be connected to the second impurity injector 159. When the thin film transistor illustrated in FIG. 10 is applied to a liquid crystal display, a transparent pixel electrode is connected to the drain electrode 176.
    [41] The operation of the thin film transistor according to the exemplary embodiment of the present invention having the above configuration will be briefly described with reference to FIG. 1 or FIG. 10.
    [42] First, when a predetermined voltage is applied to the data line 220 from the outside, the voltage is supplied to the first impurity injection part 153 of the active layer 157 via the source electrode 173 through the data line 220. .
    [43] In this case, the voltage supplied to the first impurity implantation unit 153 may not be applied to the semiconductor pattern unit 156 due to the high resistance of the semiconductor pattern unit 156 where the channel is not formed.
    [44] In this state, a voltage equal to or higher than a threshold voltage is applied to the gate electrode 137 through the gate line 210, and thus a channel through which electrons can move is formed in the semiconductor pattern unit 156.
    [45] As the channel is formed in the semiconductor pattern portion 156 of the active layer 157, the voltage applied to the first impurity implantation portion 153 is applied to the second impurity implantation portion 159 through the semiconductor pattern portion 156. . The voltage applied to the second impurity injector 159 is again applied to the drain electrode 176.
    [46] Hereinafter, a method of manufacturing a thin film transistor according to an embodiment of the present invention will be described with reference to the accompanying drawings.
    [47] 2 is a process diagram illustrating that a gate metal is formed on a substrate according to an embodiment of the present invention.
    [48] Referring to FIG. 2, a chromium thin film 120 is formed on a substrate 100, for example, a transparent substrate, and an aluminum thin film 130 is formed on an upper surface of the chromium thin film 120.
    [49] Subsequently, a photoresist thin film is formed on the entire surface of the aluminum thin film 130. The photoresist thin film is left in the shape of the gate thin film at the position where the gate thin film is to be formed in the exposure process. Hereinafter, the patterned photoresist thin film will be defined as a photoresist pattern 131.
    [50] The portions of the aluminum thin film 130 and the chromium thin film 120 which are not protected by the photoresist pattern 131 are all removed by wet etching or dry etching, and the photoresist pattern 131 is removed. Is removed through an ashing process.
    [51] 3 is a process diagram illustrating a gate electrode formed on a substrate according to an embodiment of the present invention.
    [52] Referring to FIG. 3, the aluminum thin film 130 and the chromium thin film 120 are patterned to form a gate electrode 137 including a chrome pattern 125 and an aluminum pattern 135 on the substrate 100.
    [53] 4 is a process diagram illustrating an insulating film for insulating the gate electrode according to an exemplary embodiment of the present invention.
    [54] Referring to FIG. 4, an insulating layer 140 is formed over the entire surface of the substrate 100 to cover the gate electrode 137. The insulating layer 140 is formed of a nitride film (SiNx) thin film, a silicon oxide film (SiO 2 ), or the like.
    [55] FIG. 5 is a process diagram illustrating an amorphous silicon thin film and an ion stopper thin film formed on an upper surface of an insulating film according to an embodiment of the present invention.
    [56] Referring to FIG. 5, the amorphous silicon thin film 150 is formed on the substrate 100 on which the insulating film 140 is formed so that the insulating film 140 is completely covered. The ion stopper thin film 160 is again formed on the surface of the amorphous silicon thin film 150.
    [57] Like the insulating film 140, the ion stopper thin film 160 is formed of a nitride film (SiNx) thin film, a silicon oxide film (SiO 2 ), or the like.
    [58] 6 is a conceptual diagram illustrating a process of patterning an ion stopper thin film according to an embodiment of the present invention.
    [59] Referring to FIG. 6, the photoresist material is coated on the surface of the ion stopper thin film 160 by spin coating to form a photoresist thin film.
    [60] After the photoresist thin film is soft baked again, it is exposed and developed while being aligned with the pattern mask. In this case, an area not exposed by the pattern mask is an area corresponding to the upper portion of the gate electrode 137.
    [61] By exposing and developing the photoresist thin film, a photoresist pattern 161 is formed on the upper surface of the ion stopper thin film 160. In the state where the photoresist pattern 161 is formed, the substrate 100 is dry etched in the chamber in which the plasma environment is formed.
    [62] Accordingly, portions of the ion stopper thin film 160 formed on the substrate 100 that are not protected by the photoresist pattern 161 are all etched and removed by the plasma. After the ion stopper thin film 160 is etched, the photoresist pattern 161 is removed by an ashing process.
    [63] 7 is a process diagram illustrating an ion stopper patterned from an ion stopper thin film according to an embodiment of the present invention.
    [64] Referring to FIG. 7, the ion stopper 165 is formed from the ion stopper thin film 160. The ion stopper 165 is formed on the upper surface of the gate electrode 137 in a predetermined area.
    [65] The ion stopper 165 serves to prevent the accelerated ion from being injected into the amorphous silicon thin film 150 formed under the ion stopper 165.
    [66] FIG. 8 is a flowchart illustrating ion implantation performed on an amorphous silicon thin film having an ion stopper according to an embodiment of the present invention.
    [67] Referring to FIG. 8, ion implantation by accelerated ions is performed on the amorphous silicon thin film 150 having the ion stopper 165 formed thereon.
    [68] In this case, the dopant injected into the amorphous silicon thin film 150 is n + ions. In this case, n + ions are not implanted into the amorphous silicon thin film 150, which is positioned below the ion stopper 165, and are implanted only in a portion of the amorphous silicon thin film 150 that is not covered by the ion stopper 165. In this process, since the lattice structure of the amorphous silicon thin film 150 is substantially damaged, it is preferable to perform a heat treatment process after the ion implantation.
    [69] By the ion implantation process illustrated in FIG. 8, the amorphous silicon thin film 150 is divided into three regions that are electrically different from each other.
    [70] The first region is a region of the amorphous silicon thin film 150 that is covered by the ion stopper 165. This region is a region where ions are not implanted into the amorphous silicon thin film 150, and the unique characteristics of the amorphous silicon remain intact. Hereinafter, this region will be referred to by reference numeral 156 and will be referred to as a semiconductor pattern portion.
    [71] The second region and the third region are regions in which n + dopant is implanted in the amorphous silicon thin film 150. The region in which n + dopant is implanted into the amorphous silicon thin film 150 has a characteristic close to the conductor disappearing inherent semiconductor characteristics of the amorphous silicon.
    [72] The second region is a region connected to the first end 154 of the semiconductor pattern portion 156. Hereinafter, the region connected to the first end 154 will be defined as a first impurity implanted portion 152a.
    [73] The third region is a region connected to the second end 155 facing the first end 154 of the semiconductor pattern portion 156. Hereinafter, the second impurity implantation portion is a region connected to the second end 155. It is defined as (158a).
    [74] FIG. 9 is a process diagram illustrating a source / drain metal formed on an upper surface of a semiconductor pattern portion, a first impurity implanted portion, and a second impurity implanted portion according to an embodiment of the present invention.
    [75] Referring to FIG. 9, in a state where n + dopant is partially injected into the amorphous silicon thin film 150 to form the semiconductor pattern part 156, the first impurity injection part 152a, and the second impurity injection part 158a, The source / drain metal 170 is formed on the upper surface thereof again.
    [76] Subsequently, a photoresist thin film is formed on the top surface of the source / drain metal 170 using a photoresist material.
    [77] After the photoresist thin film is soft baked again, exposure and development are performed while the photoresist thin film and the pattern mask (not shown) are aligned with each other. Accordingly, the photoresist thin film is patterned to form the photoresist pattern 171. The photoresist pattern 171 is patterned in a form suitable for forming source and drain electrodes.
    [78] 10 is a flowchart illustrating a thin film transistor completed according to an embodiment of the present invention.
    [79] Referring to FIG. 10, the source / drain metal 170 is patterned by the photoresist pattern 171 to form a source electrode 173 and a drain electrode 176.
    [80] In addition, unnecessary portions of the first impurity injector 152a and the second impurity injector 158a are also patterned together with the source electrode 173 and the drain electrode 176.
    [81] Hereinafter, a new reference numeral 153 will be given to the patterned first impurity implantation unit 152a, and a new reference numeral 159 will be assigned to the patterned second impurity implantation unit 158a.
    [82] Through the process of FIGS. 2 to 9 as described above, a thin film transistor is manufactured. The thin film transistor manufactured through the above process may be applied to various devices such as a liquid crystal display device.
    [83] As described in detail above, the reliability of the thin film transistor is improved compared to the method of forming the n + amorphous silicon thin film and the amorphous silicon thin film and then patterning the n + amorphous silicon thin film or using the etch stopper to form the channel layer. Not only can it be greatly improved, but also the channel layer is formed of a single layer amorphous silicon thin film, which has the advantage of simplifying the manufacturing process.
    [84] In the detailed description of the present invention described above with reference to a preferred embodiment of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge in the scope of the invention described in the claims to be described later It will be understood that various modifications and variations can be made in the present invention without departing from the scope of the present invention.
    权利要求:
    Claims (8)
    [1" claim-type="Currently amended] A plurality of gate electrodes formed on the substrate;
    A semiconductor pattern part formed on the gate electrode so as to be insulated from the gate electrode, a first impurity injection part for supplying electrons to the semiconductor pattern part, and a second impurity injection part receiving the electrons from the semiconductor pattern part; Active layer;
    An impurity implantation blocking pattern disposed on the semiconductor pattern portion;
    A source electrode connected to the first impurity injector; And
    And a drain electrode connected to the second impurity injector.
    [2" claim-type="Currently amended] The thin film transistor of claim 1, wherein the active layer is formed of an amorphous silicon material.
    [3" claim-type="Currently amended] The thin film transistor of claim 1, wherein n + dopant is implanted into the first impurity implantation unit and the second impurity implantation unit.
    [4" claim-type="Currently amended] The thin film transistor of claim 1, further comprising an insulating layer between the semiconductor pattern part, the first impurity injecting part, the second impurity injecting part, and the gate electrode.
    [5" claim-type="Currently amended] Forming a plurality of gate electrodes on the substrate;
    An active pattern including a semiconductor pattern portion formed on the gate electrode so as to be insulated from the gate electrode, a first impurity injection portion supplying electrons to the semiconductor pattern portion, and a second impurity injection portion receiving the electrons from the semiconductor pattern portion Forming a layer;
    Forming a source electrode connected to the first impurity injector and a drain electrode connected to the second impurity injector.
    [6" claim-type="Currently amended] The method of claim 5, wherein the forming of the active layer comprises: forming an amorphous silicon thin film on an upper surface of the gate electrode to be insulated from the gate electrode;
    Forming an ion stopper pattern on an upper surface of the gate electrode of the amorphous silicon thin film; And
    A first n + dopant is injected into the entire surface of the amorphous silicon thin film on which the ion stopper pattern is formed, and is connected to the semiconductor pattern portion and the first end of the semiconductor pattern portion below the ion stopper pattern to supply electrons to the semiconductor pattern portion; And forming a second impurity injecting part connected to the impurity injecting part and the second end of the semiconductor pattern part to receive the electrons from the semiconductor pattern part.
    [7" claim-type="Currently amended] 6. The method of claim 5, further comprising forming an insulating layer for insulating the gate electrode and the channel layer before forming the active layer. 7.
    [8" claim-type="Currently amended] The method of claim 5, further comprising heat treating the active layer after forming the active layer.
    类似技术:
    公开号 | 公开日 | 专利标题
    US9368637B2|2016-06-14|Thin film transistor and manufacturing method thereof, array substrate and display device
    KR101213708B1|2012-12-18|Array substrate and method of fabricating the same
    KR100485531B1|2005-04-27|Poly silicon TFT and method for fabricating of the same
    US5612234A|1997-03-18|Method for manufacturing a thin film transistor
    US6878584B2|2005-04-12|Flat panel display with high capacitance and method of manufacturing the same
    KR100437475B1|2004-06-23|Method for fabricating display device used in flat display device
    US6335290B1|2002-01-01|Etching method, thin film transistor matrix substrate, and its manufacture
    US6757031B2|2004-06-29|Metal contact structure and method for thin film transistor array in liquid crystal display
    KR940007451B1|1994-08-18|Fabricating method of thin film transistor
    US6197625B1|2001-03-06|Method of fabricating a thin film transistor
    KR0156202B1|1998-11-16|Liquid crystal display device and its manufacturing method
    JP3946545B2|2007-07-18|Method for manufacturing CMOS thin film transistor
    EP0217406B1|1992-06-10|Thin-film transistor and method of fabricating the same
    US6440784B2|2002-08-27|Thin film transistor and a fabricating method thereof
    US7402468B2|2008-07-22|Flat panel display and method of fabricating the same
    JP5128947B2|2013-01-23|Amorphous silicon thin film transistor and manufacturing method thereof
    US6362028B1|2002-03-26|Method for fabricating TFT array and devices formed
    US5010027A|1991-04-23|Method for fabricating a self-aligned thin-film transistor utilizing planarization and back-side photoresist exposure
    US20060267097A1|2006-11-30|Method for forming a MOS transistor and structure thereof
    US7482208B2|2009-01-27|Thin film transistor array panel and method of manufacturing the same
    KR100387122B1|2003-06-12|Fabrication Method of Poly-Si Thin Film Transistor Having Back Bias Effects
    US7061019B2|2006-06-13|Semiconductor circuit array substrate with a photo-electric sensor portion
    US6998640B2|2006-02-14|Thin film transistor structure
    KR100259078B1|2000-06-15|Thin film transistor and method fabricating the same
    US6537843B2|2003-03-25|Thin film transistor and method of manufacturing the same
    同族专利:
    公开号 | 公开日
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2002-11-21|Application filed by 삼성전자주식회사
    2002-11-21|Priority to KR1020020072876A
    2004-05-31|Publication of KR20040044726A
    优先权:
    申请号 | 申请日 | 专利标题
    KR1020020072876A|KR20040044726A|2002-11-21|2002-11-21|Thin film transistor and method for manufacturing thereof|
    [返回顶部]